1. Field of the Invention
This invention relates to an electrically rewritable and non-volatile semiconductor memory device (EEPROM).
2. Description of Related Art
An EEPROM flash memory is usually formed to have an erase unit larger than read or write unit, and this may cause the occupied area of decoders to be lessened. For example, a NAND-type flash memory has NAND cell units arranged therein, which constitute a cell array, each NAND cell unit having plural memory cell connected in series. Data erase is performed by a block which is defined as a set of NAND cell units arranged along a word line, while data read or write is performed by a page which is defined as a set of memory cells arranged along a word line.
The NAND-type flash memory is made to have a small unit cell size because plural memory cells which constitute a NAND cell unit are connected in series in such a manner that adjacent two memory cells share a source/drain diffusion layer. Further, the NAND-type flash memory device has a page buffer, which is possible to store read data or write data of one page (e.g., 512 Byte), and data input/output between the page buffer and I/O ports are serially transferred by a byte. Based on these features, the NAND-type flash memory shows a high performance when it is applied to, for example, electric cards for storing a large capacitive data such as image, animation, and music data.
To over-write data into a block, a block erase operation is automatically performed prior to the data write, following it data write is performed in the flash memory chip. To hold the data in the block to be over-written without erasing, it is required to perform a copy-write operation for transferring the data to one of other blocks (i.e., spare block) (refer to, for example, Unexamined Japanese Patent Application Publication No. 2003-233992).
It is usually a host device disposed outside of the flash memory chip that performs such a spare block management in the flash memory chip. However, the flash memory management data in the host device is not always identical with the internal state of the flash memory. For example, it may be happened an event that although the block erase has started in the flash memory in response to an instruction of the host device, the power supply is cut off, or the flash memory is drawn out from the system before completion of data erase. In this case, it will be happened a situation where in spite of that a block is designated as a spare block in the management information of the host device, it has not been erased in practice. To deal with this situation, it will be required to confirm that a spare block has been erased in practice prior to use it.
Therefore, it is necessary for the host device to send erase command and address to a flash memory prior to using a spare block therein for executing spare block erase. Such the erase sequence usually includes a pre-write or pre-program operation for reducing erase stress influences on the block prior to the block erase operation. If it is always required to adapt such the erase sequence to a spare block, which is supposed as having been erased, as it is, it will take a great time loss.